Flexible Design of Hardware-supported High-performance Protocol Processing Units

Emerging applications mostly require both, high performance as well as support of a wide variety of communication services. For example, audio, video, and data transmission may require highly different services, e.g., guaranteed delay, jitter, or bandwidth. An additional challenge arises by the growing demand for multipoint communication services. ATM networks are capable of satisfying the basic application requirements by providing multipoint bearer services with data rates exceeding a gigabit per second. However, current communication subsystems (including higher layer protocols) that provide reliable services are not able to deliver the available network performance to the applications. In order to provide the required high performance services to the applications, new protocols as well as high-performance implementation architectures for the communication subsystems need to be designed. Dedicated VLSI components should be used in flexible implementation platforms used for time-critical processing tasks in order to provide high performance. This paper presents a new approach for the flexible design of hardware-supported highperformance communication subsystems. The design process allows mapping of a formal protocol specification onto a parallel, hardware-based implementation architecture. The highly modular VLSI implementation architecture designed with parametrizable and programmable components allows for service flexibility. The architecture is not limited to a certain protocol, but allows the implementation of a variety of high-speed protocols. We validated our approach with a design example using a formal specification of the protocol RMC-AAL (Reliable Multicast ATM Adaptation Layer, RMC-AAL [CaZi95]) Design Flow One global goal of research is the automatic derivation of a high-performance communication subsystem from a formal specification [KrKS87, Kris92, Schi95]. Figure 1 shows the overall design process of our approach based on individual design steps that are customized for the design of hardware-supported high-performance ATM protocol processing units. The specification mentioned here consists of the protocol itself and a set of configuration parameters. The standardized language SDL (Specification and Description Language, [ITU88]) is used for specification. Therefore, we can use different tools for formal verification of the protocols to be implemented. The configuration parameters describe the desired performance, the existing software environment, and the maximum costs of a system. Costs may be expressed in terms of processing costs, or hardware complexity. For determination of the required number of processing units, simulation results and measurements at results of previous design cycles can be used. From these parameters, an implementation framework is composed from a set of predefined functional units. This framework consists of the interfaces to an environment, static memory for protocol data and a central crossbar to connect all components (c.f. Figure 2). We describe all hardware components shown in Figure 2 using the standardized hardware description language VHDL (VHSIC Hardware Description Language, [IEEE87]). From protocols like RMC-AAL we have extracted several functions, e.g., timer, CRC, FEC, transmit, or acknowledgement processing. These functions can be implemented on four different alternative architectures depending on the desired performance: • RISC-processors: The tool Geode [Veri95] can be used to generate C-code from an SDLspecification. A RISC-processor can execute this code after compilation. Descriptions of different RISC-processors are available for example as VHDL-code or gate-level schematic. • Synthesisable Protocol Automata (SPA): With the help of a customized SDL-to-VHDLcompiler we can automatically map an SDL-description of a protocol automaton onto a VHDL-description of a hardware unit. After synthesis onto real hardware (e.g., with the tool Synopsys) this unit acts as a protocol automaton. Due to the dedicated hardware for protocol processing, the performance of such a unit may be significantly higher compared to a general purpose RISC-processor. However, existing hardware synthesis tools do not achieve optimal performance when synthesising netlists from high-level VHDL descriptions. configuration parameters protocol